1. Technical Field
The present invention relates to a switching power source device that outputs direct current voltage, and in particular, relates to a switching power source device that includes a synchronous rectification circuit.
2. Related Art
FIG. 9 shows a configuration of heretofore known technology (Japanese Patent No. 4,158,054) of a switching power source device using a synchronous rectification circuit. The switching power source device is configured of a main switching element FET1, connected in series to a primary winding N1 of a transformer T, a snubber circuit Sn connected in parallel to the primary winding N1, a primary side control circuit 2 that drives the main switching element FET1, a synchronous rectifier switching element FET2, connected in series to a secondary winding N2 of the transformer T, a diode D connected in parallel to the synchronous rectifier switching element FET2, and a secondary side control circuit 30 that drives the synchronous rectifier switching element FET2.
The secondary side control circuit 30 has a voltage divider circuit, which divides the drain-to-source voltage of the synchronous rectifier switching element FET2 using resistors R1 and R2, and a time constant generating capacitor C, which is charged via a diode D1 and resistor R5 in accordance with the drain-to-source voltage of the synchronous rectifier switching element FET2. A discharge resistor R6 is connected in parallel to the capacitor C. Also, a NOT circuit 31, whose output is inverted when the voltage of the capacitor C reaches a predetermined threshold value, is connected to the high potential side of the capacitor C. A connection point of the resistors R1 and R2 and the output terminal of the NOT circuit 31 are connected one each to input terminals of a NOR circuit 32, and the output terminal of the NOR circuit 32 is connected to a control terminal of the synchronous rectifier switching element FET2.
A series circuit of the primary winding N1 of the transformer T and the main switching element FET1 is connected to a direct current power source Vd. Also, a parallel circuit of a smoothing capacitor Co and load Ro is connected to a series circuit of the secondary winding N2 of the transformer T and the synchronous rectifier switching element FET2.
Next, a description will be given of an operation of the switching power source device configured in this way. The main switching element FET1 carries out an on/off operation such that frequency and duty ratio vary in accordance with the output voltage, wherein, when the main switching element FET1 is turned on, current flows through the primary winding N1, and energy is accumulated in the transformer T. At the same time, voltage is generated in the secondary winding N2 such that the potential on the side connected to the drain terminal of the synchronous rectifier switching element FET2 increases. At this time, the connection point of the resistors R1 and R2 is at an H level. Also, as the capacitor C is charged, the output of the NOT circuit 31 changes from an H level to an L level. That is, the output of the NOR circuit 32 is an L level, and the synchronous rectifier switching element FET2 maintains an off-state.
Presently, the main switching element FET1 is turned off, and the secondary winding N2 discharges the energy accumulated in the transformer T through the diode D. At this time, the connection point of the resistors R1 and R2 is at an L level. Also, as the capacitor C is charged, the output of the NOT circuit 31 is an L level. That is, the output of the NOR circuit 32 is an H level, and the synchronous rectifier switching element FET2 is turned on.
As the drain-to-source voltage is practically zero for the period for which the synchronous rectifier switching element FET2 is in an on-state, the capacitor C is discharged by the resistor R6. When the voltage of the capacitor C falls below the threshold value of the NOT circuit 31, the output of the NOT circuit 31 changes from an L level to an H level. That is, the output of the NOT circuit 32 changes from an H level to an L level, and the synchronous rectifier switching element FET2 is turned off.
Thereafter, the switching power source device repeats the heretofore described operation.
In this way, as a synchronous rectification period is generated without the current flowing through the transformer T being detected directly, the switching power source device is not affected by the on-state resistance of the synchronous rectifier switching element FET2. Therefore, as it is possible to normally operate a synchronous rectifier switching element FET2 with a smaller on-state resistance, it is possible to make efficiency high.
Also, the switching power source device is such that it is possible to prevent a reverse flow of power from the direct current voltage output side by the time constant of the capacitor C being regulated, and the synchronous rectifier switching element FET2 being turned off before all the energy of the secondary winding N2 is discharged.
Furthermore, the switching power source device is such that, as the synchronous rectification period is generated by an integrator configured of the resistors R5 and R6 and capacitor C, it is possible to suppress the effect of noise.
However, the switching power source device described in Japanese Patent No. 4,158,054 is such that the capacitor C charge and discharge voltage and time differ when a different load is connected. Because of this, there is a need for threshold value regulation in order to adjust the timing at which the synchronous rectifier switching element FET2 is turned off to the timing at which the current flowing through the secondary winding N2 reaches zero. That is, it is necessary to determine the turning off timing so that the synchronous rectifier switching element FET2 can be turned off with sufficient leeway before the main switching element FET1 is next turned on. Also, as the maximum value of the capacitor C charge voltage decreases in the case of a light load, the threshold value voltage is relatively high, and the synchronous rectification period becomes shorter.